Bandpass sample-and-hold circuits are modern low-cost, high-performance solutions for directly sampling an RF signal and are often found in the front end of direct-sampling RF analog-to-digital converters (ADCs) to hold the signal steady during the conversion period for the ADC to process. Thus, many communication systems employ such circuits, including but not limited to commercial wireless communication systems.
To directly digitize a high-frequency RF signal, one solution is to use high-speed sample-and-hold circuits, which are able to track the fast-changing signal during the track period as well as to hold the sampled signal long enough during the hold period. Conventional sample-and-hold circuits are wideband sample-and-hold circuits that pass through all the signals, from DC all the way to the frequencies of interest. They not only collect all out-of-band interference but also self-generated circuit noise (including, e.g., white noise, flicker noise, shot noise, etc). When the frequencies of interest are high, the self-generated circuit noise will adversely impact the signal-to-noise ratio (SNR) of the circuit and thus limit its sample-and-hold resolution. Furthermore, to maintain the voltage gain and linearity for wide bandwidths, typical sample-and-hold circuits have to use significant power.
FIG. 1 is a schematic depiction of a typical sample-and-hold (also referred to in the art as track-and-hold) circuit architecture 100 commonly used in high-speed, wide-bandwidth applications that employs transconductance cells (or Gm-Cells) 110 that converts an input voltage to current. The skilled reader will recognize this as an open-loop track-and-hold circuit with hold signal feedback to isolate the input signal feed-through. The input signal or input voltage Vin is first converted into current Iin by a first transconductance cell 110, which is then fed through a first switch 112 and converted back to a voltage Vm by a resistor 114 having a resistance value of R. The converted voltage Vm is sampled by a second switch 116 and accumulated by a capacitor 118 having a capacitance value of C. The signal accumulated in capacitor 118 is buffered by a unity-gain amplifier/buffer 120 and subsequently fed as output voltage Vout. A second Gm cell 130 is connected between the buffered output of the buffer 120 and the first switch 112 to stabilize the accumulated signal during the circuit's HOLD mode (i.e. while the converted voltage Vm is not being accumulated). The use of the second Gm cell 130 also decouples the leak-through noise from the input caused by the parasitic capacitance present in the second switch 116.
In this circuit architecture the voltage gain of the circuit is defined by the transconductance gain of the first Gm cell 110 and the resistance value R of the resistor 114. The bandwidth is determined by R, C and the bias current of the second switch 116. To present a wider operational bandwidth, R and C need to be reduced. However, a small R value will produce a small converted voltage Vm and therefore will necessitate a higher transconductance gain from the first Gm cell 110 to compensate, which in turn will lead to higher overall power consumption by the circuit. On the other hand, a low value of C will cause more KT/C switching noise and also a worse droop rate because the signal Vm cannot be held steady, thereby causing error. Conversely, a higher value of C will require a higher bias current for the second switch 116 to charge, to discharge, and to minimize signal distortion. Thus, to sample and hold very high frequency, this circuit architecture requires comparatively large amounts of power.
In addition to less-than-optimal power consumption, this wideband sample-and-hold circuit architecture also presents excessive noise collection because it collects all out-of-band interference along with the self-generated circuit noise (white, flicker, shot noise, etc), leading to the reduced SNR performance and attendant limited resolution previously mentioned.
What is now needed is an improved archotecture for wideband sample-and-hold circuits that offer improved SNR performance and higher sampling resolution. The embodiments of the present disclosure answer these and other needs.